© 1998
PRELIMINARY DATA SHEET
FEATURE
• Ultra super mini-mold thin flat package
(1.4 mm × 1.8 mm × 0.59 mm: TYP.)
• Contains same chip as 2SC5008
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
PARAMETER SYMBOL RATING UNIT
Collector to Base Voltage VCBO 20 V
Collector to Emitter Voltage VCEO 10 V
Emitter to Base Voltage VEBO 1.5 V
Collector Current IC 35 mA
Total Power Dissipation PT 125 mW
Junction Temperature Tj 150 °C
Storage Temperature Tstg –65 to +150 °C
SILICON TRANSISTOR
2SC5434
NPN EPITAXIAL SILICON TRANSISTOR
FOR HIGH-FREQUENCY LOW-NOISE AMPLIFICATION
Document No. P13145EJ1V0DS00 (1st edition)
Date Published February 1998 N CP(K)
Printed in Japan
PACKAGE DIMENSIONS (in mm)
1.4 ± 0.05
0.8 ± 0.1
1.4 ± 0.1
0.59 ± 0.05
(0.9)
0.45
0.45
+0.1 –0
0.3
+0.1 –0.05
0.15
+0.1 –0
0.2
1
3
2
T H
PIN CONNECTIONS
1: Emitter
2: Base
3: Collector
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Collector Cut-off Current ICBO VCB = 10 V, IE = 0 1000 nA
Emitter Cut-off Current IEBO VEB = 1 V, IC = 0 1000 nA
DC Current Gain hFE VCE = 3 V, IC = 5 mA
Note 1
80 145
Gain Bandwidth Product fT VCE = 3 V, IC = 5 mA, f = 2 GHz 5.5 80 GHz
Reverse Transfer Capacitance Cre VCB = 3 V, IE = 0, f = 1 MHz
Note 2
0.3 0.7 pF
Insertion Power Gain |S21e|
2
VCE = 3 V, IC = 5 mA, f = 2 GHz 5.5 7.5 dB
Noise Figure NF VCE = 3 V, IC = 5 mA, f = 2 GHz 1.9 3.2 dB
Notes 1. Pulse measurement PW ≤ 350 µs, duty cycle ≤ 2 %
2. Collector to base capacitance measured by capacitance meter (automatic balance bridge method) when
emitter pin is connected to the guard pin.
Because this product uses high-frequency process, avoid excessive input of static electricity, etc.
The information in this document is subject to change without notice.