© 1998
PRELIMINARY DATA SHEET
FEATURE
• Ultra super mini-mold thin flat package
(1.4 mm × 0.8 mm × 0.59 mm: TYP.)
• Contains same chip as 2SC5195
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
PARAMETER SYMBOL RATING UNIT
Collector to Base Voltage VCBO 9V
Collector to Emitter Voltage VCEO 6V
Emitter to Base Voltage VEBO 2V
Collector Current IC 100 mA
Total Power Dissipation PT 125 mW
Junction Temperature Tj 150 °C
Storage Temperature Tstg –65 to +150 °C
SILICON TRANSISTOR
2SC5437
NPN EPITAXIAL SILICON TRANSISTOR
FOR HIGH-FREQUENCY LOW-NOISE AMPLIFICATION
Document No. P13146EJ1V0DS00 (1st edition)
Date Published February 1998 N CP(K)
Printed in Japan
PACKAGE DIMENSIONS (in mm)
1.4 ± 0.05
0.8 ± 0.1
1.4 ± 0.1
0.59 ± 0.05
(0.9)
0.45
0.45
+0.1 –0
0.3
+0.1 –0.05
0.15
+0.1 –0
0.2
1
3
2
T S
PIN CONNECTIONS
1: Emitter
2: Base
3: Collector
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Collector Cut-off Current ICBO VCB = 5 V, IE = 0 100 nA
Emitter Cut-off Current IEBO VEB = 1 V, IC = 0 100 nA
DC Current Gain hFE VCE = 1 V, IC = 3 mA
Note 1
80 145
Reverse Transfer Capacitance Cre VCB = 1 V, IE = 0, f = 1 MHz
Note 2
0.7 0.8 pF
Gain Bandwidth Product (1) fT (1) VCE = 1 V, IC = 3 mA, f = 2 GHz 4.0 5.0 GHz
Gain Bandwidth Product (2) fT (2) VCE = 3 V, IC = 20 mA, f = 2 GHz 9.5 GHz
Insertion Power Gain (1) |S21e|
2
(1) VCE = 1 V, IC = 3 mA, f = 2 GHz 3.0 4.0 dB
Insertion Power Gain (2) |S21e|
2
(2) VCE = 3 V, IC = 20 mA, f = 2 GHz 8.0 dB
Noise Figure (1) NF (1) VCE = 1 V, IC = 3 mA, f = 2 GHz 1.9 2.5 dB
Noise Figure (2) NF (2) VCE = 3 V, IC = 7 mA, f = 2 GHz 1.7 dB
Notes 1. Pulse measurement PW ≤ 350 µs, duty cycle ≤ 2 %
2. Collector to base capacitance measured by capacitance meter (automatic balance bridge method) when
emitter pin is connected to the guard pin.
Because this product uses high-frequency process, avoid excessive input of static electricity, etc.
The information in this document is subject to change without notice.