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2N5638

器件描述:N-Channel Switch
器件厂商:FAIRCHILD [Fairchild Semiconductor]
文件大小:26.29KB,共3页
Sponsor by e络盟
器件资料摘要:
©2002 Fairchild Semiconductor Corporation Rev. A1, November 2002
2N56
38
TO-92
Absolute Maximum Ratings * T
C
=25°C unless otherwise noted
* These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1. These ratings are based on a maximum junction temperature of 150 degrees C.
2. These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Electrical Characteristics T
C
=25°C unless otherwise noted
* Pulse Test: Pulse Width ≤ 300µs, Duty Cycle ≤ 1.0%
Thermal Characteristics T
A
=25°C unless otherwise noted
Symbol Parameter Value Units
V
DG
Drain-Gate Voltage 30 V
V
GS
Gate-Source Voltage -30 V
I
GF
Forward Gate Current 50 mA
T
J
, T
STG
Operating and Storage Junction Temperature Range -55 ~ +150 °C
Symbol Parameter Test Condition Min. Typ. Max. Units
Off Characteristics
V
(BR)GSS
Gate-Source Breakdown Voltage V
DS
= 0, I
G
= -10µA-30 V
I
GSS
Gate Reverse Current V
GS
= -15V, V
DS
= 0 -1.0 nA
I
D(off)
Drain Cutoff Leakage Current V
DS
= 12V, V
GS
= 15V 1.0 nA
On Characteristics
I
DSS
Zero-Gate Voltage Drain Current * V
DS
= 20V, I
GS
= 0 50 mA
r
DS(on)
Drain-Source On Resistance V
GS
= 0V, I
D
= 1.0mA 30 Ω
Small Signal Characteristics
r
ds(on)
Drain-Source On Resistance V
DS
= V
GS
= 0, f = 1.0kHz 30 Ω
C
iss
Input Capacitance V
DS
= 0, V
GS
= 12V, f = 1.0MHz 10 pF
C
rss
Reverse Transfer Capacitance V
DS
= 0V, V
GS
= 12V, f = 1.0MHz 4.0 pF
Switching Characteristics
t
d(on)
Trun On Delay Time V
DD
= 10V, V
GS(on)
= 0
V
GS(off)
= -12, I
D(on)
= 12mA
R
G
= 50Ω
4.0 ns
t
r
Rise Time 5.0 ns
t
d(off)
Trun Off Delay Time 5.0 ns
t
f
Fall Time 10 ns
Symbol Parameter Max. Units
P
D
Total Device Dissipation
Derate above 25°C
350
2.8
mW
mW/°C
R
θJC
Thermal Resistance, Junction to Case 125 °C/W
R
θJA
Thermal Resistance, Junction to Ambient 357 °C/W
2N5638
N-Channel Switch
• This device is designed for low level analog switchng, sample and hold
circuits and chopper stabilized amplifiers.
• Sourced from process 51.
1. Drain 2. Source 3. Gate
1