E
PRELIMINARY
July 1997 Order Number: 290530-005
c110 Intel SmartVoltage Technology
 5V or 12V Program/Erase
 2.7V, 3.3V or 5V Read Operation
 Increased Programming Throughput
at 12V V
PP
c110 Very High-Performance Read
 5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
 3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
 2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
c110 Low Power Consumption
 Max 60 mA Read Current at 5V
 Max 30 mA Read Current at
2.7V–3.6V
c110 x8/x16-Selectable Input/Output Bus
 28F400 for High Performance 16- or
32-bit CPUs
c110 x8-Only Input/Output Architecture
 28F004B for Space-Constrained
8-bit Applications
c110 Optimized Array Blocking Architecture
 One 16-KB Protected Boot Block
 Two 8-KB Parameter Blocks
 One 96-KB Main Block
 Three 128-KB Main Blocks
 Top or Bottom Boot Locations
c110 Absolute Hardware-Protection for Boot
Block
c110 Software EEPROM Emulation with
Parameter Blocks
c110 Extended Temperature Operation
 –40°C to +85°C
c110 Extended Cycling Capability
 100,000 Block Erase Cycles
(Commercial Temperature)
 10,000 Block Erase Cycles
(Extended Temperature)
c110 Automated Word/Byte Program and
Block Erase
 Industry-Standard Command User
Interface
 Status Registers
 Erase Suspend Capability
c110 SRAM-Compatible Write Interface
c110 Automatic Power Savings Feature
 1 mA Typical I
CC
Active Current in
Static Operation
c110 Reset/Deep Power-Down Input
 0.2 µA I
CC
Typical
 Provides Reset for Boot Operations
c110 Hardware Data Protection Feature
 Write Lockout during Power
Transitions
c110 Industry-Standard Surface Mount
Packaging
 40-Lead TSOP
 44-Lead PSOP: JEDEC ROM
Compatible
 48-Lead TSOP
 56-Lead TSOP
c110 Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
c110 ETOX™ IV Flash Technology
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B