1
CAT28C256
32K-Bit Parallel E
2
PROM
FEATURES
n Fast Read Access Times: 120/150ns
n Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 150 µA Max.
n Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
n Fast Write Cycle Time:
–5ms Max
n CMOS and TTL Compatible I/O
n Hardware and Software Write Protection
n Automatic Page Write Operation:
–1 to 64 Bytes in 5ms
–Page Load Timer
n End of Write Detection:
–Toggle Bit
–DATA Polling
n 100,000 Program/Erase Cycles
n 100 Year Data Retention
n Commerical, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel E
2
PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
CC
power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
The CAT28C256 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH VOLTAGE
GENERATOR
A
6
–A
14
CE
OE
WE
A
0
–A
5
I/O
0
–I/O
7
I/O BUFFERS
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
V
CC
DATA POLLING
AND
TOGGLE BIT
Doc. No. 25020-0A 2/98