26LS32
器件描述：QUAD EIA-422/3 LINE RECEIVER WITH THREE.STATE OUTPUTS
器件厂商：MOTOROLA [Motorola, Inc]
文件大小：81.17KB，共4页
Sponsor by e络盟器件资料摘要：
C0065C0077C0050C0054C0076C0083C0051C0050
SEMICONDUCTOR
TECHNICAL DATA
QUAD EIA–422/3 LINE
RECEIVER WITH
THREE–STATE OUTPUTS
ORDERING INFORMATION
PIN CONNECTIONS
Order this document by AM26LS32/D
PC SUFFIX
PLASTIC PACKAGE
CASE 648
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16)
Device
Operating
Temperature Range Package
AM26LS32PC
MC26LS32D*
T
A
= 0 to 70°C
Plastic DIP
SO–16
9
–
+
–
8
7
6
5
4
3
2
1
10
11
12
13
14
+
–
+
–
Inputs A
+
V
CC
16
3–State
Control
GND
Output B
Output D
15
3–State
Control
Inputs C
Inputs B
Inputs D
Outputs A
Output C
1
MOTOROLA ANALOG IC DEVICE DATA
C0081C0085C0065C0068 C0069C0073C0065C0045C0052C0050C0050C0047C0052C0050C0051 C0076C0105C0110C0101
C0082C0101C0099C0101C0105C0118C0101C0114 C0119C0105C0116C0104 C0084C0104C0114C0101C0101C0045C0083C0116C0097C0116C0101
C0079C0117C0116C0112C0117C0116C0115
Motorola′s Quad EIA–422/3 Receiver features four independent receiver
chains which comply with EIA Standards for the Electrical Characteristics of
Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs
are 74LS compatible, three–state structures which are forced to a high
impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP
device buffers each output control pin to assure minimum loading for either
Logic “1” or Logic “0” inputs. In addition, each receiver chain has internal
hysteresis circuitry to improve noise margin and discourage output instability
for slowly changing input waveforms. A summary of AM26LS32 features
include:
• Four Independent Receiver Chains
• Three–State Outputs
• High Impedance Output Control Inputs
(PIA Compatible)
• Internal Hysteresis – 30 mV (Typical) @ Zero Volts Common Mode
• Fast Propagation Times – 25 ns (Typical)
• TTL Compatible
• Single 5.0 V Supply Voltage
• Fail–Safe Input–Output Relationship. Output Always High When Inputs
Are Open, Terminated or Shorted
• 6.0 k Minimum Input Impedance
* Note that the surface mount MC26LS32D device uses the same die as in the plastic DIP
* AM26LS32DC device, but with an MC prefix to prevent confusion with the package suffix.
Representative Block Diagram
Hysteresis
Amplifier
Amplifier
Three–State
Control
Inputs Output
Differential
Inputs
Input
Network
Level
Translator
Level
Translator
Motorola, Inc. 1995
SEMICONDUCTOR
TECHNICAL DATA
QUAD EIA–422/3 LINE
RECEIVER WITH
THREE–STATE OUTPUTS
ORDERING INFORMATION
PIN CONNECTIONS
Order this document by AM26LS32/D
PC SUFFIX
PLASTIC PACKAGE
CASE 648
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16)
Device
Operating
Temperature Range Package
AM26LS32PC
MC26LS32D*
T
A
= 0 to 70°C
Plastic DIP
SO–16
9
–
+
–
8
7
6
5
4
3
2
1
10
11
12
13
14
+
–
+
–
Inputs A
+
V
CC
16
3–State
Control
GND
Output B
Output D
15
3–State
Control
Inputs C
Inputs B
Inputs D
Outputs A
Output C
1
MOTOROLA ANALOG IC DEVICE DATA
C0081C0085C0065C0068 C0069C0073C0065C0045C0052C0050C0050C0047C0052C0050C0051 C0076C0105C0110C0101
C0082C0101C0099C0101C0105C0118C0101C0114 C0119C0105C0116C0104 C0084C0104C0114C0101C0101C0045C0083C0116C0097C0116C0101
C0079C0117C0116C0112C0117C0116C0115
Motorola′s Quad EIA–422/3 Receiver features four independent receiver
chains which comply with EIA Standards for the Electrical Characteristics of
Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs
are 74LS compatible, three–state structures which are forced to a high
impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP
device buffers each output control pin to assure minimum loading for either
Logic “1” or Logic “0” inputs. In addition, each receiver chain has internal
hysteresis circuitry to improve noise margin and discourage output instability
for slowly changing input waveforms. A summary of AM26LS32 features
include:
• Four Independent Receiver Chains
• Three–State Outputs
• High Impedance Output Control Inputs
(PIA Compatible)
• Internal Hysteresis – 30 mV (Typical) @ Zero Volts Common Mode
• Fast Propagation Times – 25 ns (Typical)
• TTL Compatible
• Single 5.0 V Supply Voltage
• Fail–Safe Input–Output Relationship. Output Always High When Inputs
Are Open, Terminated or Shorted
• 6.0 k Minimum Input Impedance
* Note that the surface mount MC26LS32D device uses the same die as in the plastic DIP
* AM26LS32DC device, but with an MC prefix to prevent confusion with the package suffix.
Representative Block Diagram
Hysteresis
Amplifier
Amplifier
Three–State
Control
Inputs Output
Differential
Inputs
Input
Network
Level
Translator
Level
Translator
Motorola, Inc. 1995