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FM24C256 rev. B.3
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
June 2000
© 2000 Fairchild Semiconductor International
FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description
The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended IIC 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.
The entire memory array can be write disabled (Write Protection)
by connecting the WP pin to V
CC
.
Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.
The IIC communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Block Diagram
Features
a73 Extended Operating Voltages
— C256: 4.5V - 5.5V
— C256L: 2.7V - 5.5V
— C256LZ: 2.7V - 5.5V
a73 Low Power CMOS
— 1mA active current typical
— C256/C256L: 10µA standby current typical
— C256LZ: less than 1µA standby current
a73 2-wire IIC serial interface
a73 64 byte page write mode
a73 Max write cycle time of 6ms byte/page
a73 40 years data retention
a73 Endurance: 100,000 data changes
a73 Hardware write protect for entire array
a73 Schmitt trigger inputs for noise suppression
a73 Electrostatic discharge protection > 4000V
a73 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory
for CSP package availability
DS800023-1
H.V. GENERATION
TIMING &CONTROL
E
2
PROM
ARRAY
YDEC
DATA REGISTER
XDEC
CONTROL
LOGIC
WORD
ADDRESS
COUNTER
SLAVE ADDRESS
REGISTER &
COMPARATOR
START
STOP
LOGIC
WRITE
LOCKOUT
START CYCLE
CK
D
IN
R/W
LOAD INC
SDA
SCL
WP
V
CC
D
OUT
A2
A1
A0