ST24C16, ST25C16
ST24W16, ST25W16
16 Kbit Serial I
2
C Bus EEPROM
with User-Defined Block Write Protection
February 1999 1/17
AI00866B
2
PB0-PB1 SDA
V
CC
ST24x16
ST25x16
MODE/WC*
SCL
V
SS
PRE
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I
2
C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers a range of 16 Kbit I
2
C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
PRE Write Protect Enable
PB0, PB1 Protect Block Select
SDA Serial Data Address Input/Output
SCL Serial Clock
MODE
Multybyte/Page Write Mode
(C version)
WC Write Control (W version)
V
CC
Supply Voltage
VSS Ground
Table 1. Signal Names
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Note: WC signal is only available for ST24/25W16 products.