24C128
器件描述：131,072-bit 2-WIRE SERIAL CMOS EEPROM
器件厂商：ISSI [Integrated Silicon Solution, Inc]
厂商主页：http://www.issi.com/
文件大小：53.2KB，共12页
Sponsor by e络盟器件资料摘要：
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
PRELIMINARY INFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
®
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this speci fication and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
131,072-bit 2-WIRE SERIAL
CMOS EEPROM
FEATURES
• Organization:
– 16K-bit x 8-bit
64-Byte Page Write Buffer
Two-Wire Serial Interface
– Bi-directional data transfer protocol
Low Power CMOS Technology
– Active Current less than 2 mA (5V)
– Standby Current less than 5 µA (5V)
– Standby Current less than 2 µA (2.5V)
Low Voltage Operation
– IS24C128-2: Vcc = 1.8V to 5.5V
– IS24C128-3: Vcc = 2.5V to 5.5V
400 KHz (I
2
C Protocol) Compatibility
PRELIMINARY INFORMATION
MARCH 2003
Hardware Data Protection
– Write Protect pin
Sequential Read Feature
Filtered Inputs for Noise Suppression
Self time Write cycle with auto clear
– 5 ms @ 2.5V
High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 40 Years
Commercial and Industrial temperature ranges
8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP
The IS24C128 is an electrically erasable PROM
device that uses the standard 2-wire interface for
communications. The IS24C128 contains a memory
array of 128K-bits (16,384 x 8), and is further
subdivided into 256 pages of 64 bytes each for page-
write mode. This EEPROM is offered in wide operating
voltages of 1.8V to 5.5V (IS24C128-2) and 2.5V to 5.5V
(IS24C128-3) to be compatible with most application
voltages. ISSI designed the IS24C128 to be a low-cost
and low-power 2-wire EEPROM solution. The devices
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
TSSOP.
The IS24C128 maintains compatibility with the popular
2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master
device such as a microcontroller is usually connected
to one or more Slave devices such as the IS24C128.
The bit stream over the SDA line includes a series of
bytes, which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C128 has a
Write Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
DESCRIPTION
PRELIMINARY INFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
®
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this speci fication and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
131,072-bit 2-WIRE SERIAL
CMOS EEPROM
FEATURES
• Organization:
– 16K-bit x 8-bit
64-Byte Page Write Buffer
Two-Wire Serial Interface
– Bi-directional data transfer protocol
Low Power CMOS Technology
– Active Current less than 2 mA (5V)
– Standby Current less than 5 µA (5V)
– Standby Current less than 2 µA (2.5V)
Low Voltage Operation
– IS24C128-2: Vcc = 1.8V to 5.5V
– IS24C128-3: Vcc = 2.5V to 5.5V
400 KHz (I
2
C Protocol) Compatibility
PRELIMINARY INFORMATION
MARCH 2003
Hardware Data Protection
– Write Protect pin
Sequential Read Feature
Filtered Inputs for Noise Suppression
Self time Write cycle with auto clear
– 5 ms @ 2.5V
High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 40 Years
Commercial and Industrial temperature ranges
8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP
The IS24C128 is an electrically erasable PROM
device that uses the standard 2-wire interface for
communications. The IS24C128 contains a memory
array of 128K-bits (16,384 x 8), and is further
subdivided into 256 pages of 64 bytes each for page-
write mode. This EEPROM is offered in wide operating
voltages of 1.8V to 5.5V (IS24C128-2) and 2.5V to 5.5V
(IS24C128-3) to be compatible with most application
voltages. ISSI designed the IS24C128 to be a low-cost
and low-power 2-wire EEPROM solution. The devices
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
TSSOP.
The IS24C128 maintains compatibility with the popular
2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master
device such as a microcontroller is usually connected
to one or more Slave devices such as the IS24C128.
The bit stream over the SDA line includes a series of
bytes, which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C128 has a
Write Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
DESCRIPTION