1
Features
• Low-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 131,072 x 8
2-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
400 kHz (2.7V) and 1 MHz (5V) Clock Rate
Write Protect Pin for Hardware and Software Data Protection
256-byte Page Write Mode (Partial Page Writes Allowed)
Random and Sequential Read Modes
Self-timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 100,000 Write Cycles/Page
– Data Retention: 40 Years
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGA
TM
Packages
Description
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA
packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
2-wire Serial
EEPROM
1M (131,072 x 8)
AT24C1024
Rev. 1471H–SEEPR–03/03
Pin Configurations
Pin Name Function
A1 Address Input
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-lead PDIP
1
2
3
4
8
7
6
5
NC
A1
NC
GND
VCC
WP
SCL
SDA
8-lead Leadless Array

Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
NC
A1
NC
GND
8-lead SOIC
1
2
3
4
8
7
6
5
NC
A1
NC
GND
VCC
WP
SCL
SDA
8-ball dBGA
Bottom View
VCC
WP
SCL
SDA
NC
A1
NC
GND
1
2
3
4
8
7
6
5