ST24C08, ST25C08
ST24W08, ST25W08
8 Kbit Serial I
2
C Bus EEPROM
with User-Defined Block Write Protection
February 1999 1/16
AI00860E
E SDA
V
CC
ST24x08
ST25x08
MODE/WC*
SCL
V
SS
PRE
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x08 versions
– 2.5V to 5.5V for ST25x08 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W08 and ST25W08
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I
2
C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES)
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers a range of 8 Kbits I
2
C bus
EEPROM products, the ST24/25C08 and the
ST24/25W08. In the text, products are referred to
as ST24/25x08, where "x" is: "C" for Standard
version and "W" for Hardware Write Control ver-
sion.
PRE Write Protect Enable
E Chip Enable Input
SDA Serial Data Address Input/Output
SCL Serial Clock
MODE
Multibyte/Page Write Mode
(C version)
WC Write Control (W version)
V
CC
Supply Voltage
VSS Ground
Table 1. Signal Names
8
1
SO8 (M)
150mil Width
8
1
PSDIP8 (B)
0.25mm Frame
Note: WC signal is only available for ST24/25W08 products.