74AC74MTC
器件描述：Dual D-Type Positive Edge-Triggered Flip-Flop
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：104.16KB，共9页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS009920 www.fairchildsemi.com
November 1988
Revised November 1999
7
4
AC
7
4
• 74ACT74
Dual
D
-
T
y
pe Posit
i
ve Edge-
T
ri
ggered Fl
ip-
F
lop
74AC74 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
a73 I
CC
reduced by 50%
a73 Output source/sink 24 mA
a73 ACT74 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs
November 1988
Revised November 1999
7
4
AC
7
4
• 74ACT74
Dual
D
-
T
y
pe Posit
i
ve Edge-
T
ri
ggered Fl
ip-
F
lop
74AC74 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
a73 I
CC
reduced by 50%
a73 Output source/sink 24 mA
a73 ACT74 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs