100398
器件描述：Quad Differential ECL/TTL Translating Transceiver with Latch
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：117.87KB，共13页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS010970 www.fairchildsemi.com
February 1992
Revised August 2000
1
00398 Q
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ECL/
TTL T
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wi
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100398
Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
The 100398 is a quad latched transceiver designed to con-
vert TTL logic levels to differential F100K ECL logic levels
and vice versa. This device was designed with the capabil-
ity of driving a differential 25Ω ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100398 is ideal for
mixed technology applications utilizing either an ECL or
TTL backplane.
The direction of translation is set by the direction control
pin (DIR). The DIR pin on the 100398 accepts TTL logic
levels. A TTL LOW on DIR sets up the ECL pins as inputs
and TTL pins as outputs. A TTL HIGH on DIR sets up the
TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL
output in a cut-off state and the TTL outputs at a high
impedance level. A HIGH on the latch enable input (LE)
latches the data at both inputs even though only one output
is enabled at the time. A LOW on LE makes the latch trans-
parent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100398 is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All Inputs have
50 kΩ pull-down resistors.
Features
a73 Differential ECL input/output structure
a73 64 mA FAST TTL outputs
a73 25Ω differential ECL outputs with cut-off
a73 Bi-directional translation
a73 2000V ESD protection
a73 Latched outputs
a73 3-STATE outputs
a73 Voltage compensated operating range = −4.2V to −5.7V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FAST is a registered trademark of Fairchild Semiconductor.
Order Number Package Number Package Description
100398PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100398QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100398QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
February 1992
Revised August 2000
1
00398 Q
u
ad
Di
ff
erent
i
al
ECL/
TTL T
r
ansl
ati
ng T
r
ansc
eiver
wi
th Latch
100398
Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
The 100398 is a quad latched transceiver designed to con-
vert TTL logic levels to differential F100K ECL logic levels
and vice versa. This device was designed with the capabil-
ity of driving a differential 25Ω ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100398 is ideal for
mixed technology applications utilizing either an ECL or
TTL backplane.
The direction of translation is set by the direction control
pin (DIR). The DIR pin on the 100398 accepts TTL logic
levels. A TTL LOW on DIR sets up the ECL pins as inputs
and TTL pins as outputs. A TTL HIGH on DIR sets up the
TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL
output in a cut-off state and the TTL outputs at a high
impedance level. A HIGH on the latch enable input (LE)
latches the data at both inputs even though only one output
is enabled at the time. A LOW on LE makes the latch trans-
parent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100398 is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All Inputs have
50 kΩ pull-down resistors.
Features
a73 Differential ECL input/output structure
a73 64 mA FAST TTL outputs
a73 25Ω differential ECL outputs with cut-off
a73 Bi-directional translation
a73 2000V ESD protection
a73 Latched outputs
a73 3-STATE outputs
a73 Voltage compensated operating range = −4.2V to −5.7V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FAST is a registered trademark of Fairchild Semiconductor.
Order Number Package Number Package Description
100398PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100398QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100398QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)