© 2000 Fairchild Semiconductor Corporation DS010611 www.fairchildsemi.com
March 1998
Revised August 2000
1
00360 Low
Power Dual Pari
ty Checker
/Gener
ator
100360
Low Power Dual Parity Checker/Generator
General Description
The 100360 is a dual parity checker/generator. Each half
has nine inputs; the output is HIGH when an even number
of inputs are HIGH. One of the nine inputs (I
a
or I
b
) has the
shorter through-put delay and is therefore preferred as the
expansion input for generating parity for 16 or more bits.
The 100360 also has a Compare (C) output which allows
the circuit to compare two 8-bit words. The C output is
LOW when the two words match, bit for bit. All inputs have
50 kΩ pull-down resistors.
Features
a73 Lower power than 100160
a73 2000V ESD protection
a73 Pin/function compatible with 100160
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Min to Max propagation delay 35% tighter than 100160
a73 Available to industrial grade temperature range

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Truth Table
(Each Half)
Comparator Function
C = (I
0a
⊕ I
1a
) + (I
2a
⊕ I
3a
) + (I
4a
⊕ I
5a
) + (I
6a
⊕ I
7a
) +
(I
0b
⊕ I
1b
) + (I
2b
⊕ I
3b
) + (I
4b
⊕ I
5b
) + (I
6b
⊕ I
7b
)
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
100360PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100360QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100360QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
I
a
, I
b
, I
na
, I
nb
Data Inputs
Z
a
, Z
b
Parity Odd Outputs
C Compare Output
Sum of Output
HIGH Inputs Z
Even HIGH
Odd LOW