© 2000 Fairchild Semiconductor Corporation DS009882 www.fairchildsemi.com
July 1988
Revised August 2000
1
00353 Low
Power 8-Bi
t Regis
t
er
100353
Low Power 8-Bit Register
General Description
The 100353 contains eight D-type edge triggered, master/
slave flip-flops with individual inputs (D
n
), true outputs (Q
n
),
a clock input (CP), and a common clock enable pin (CEN).
Data enters the master when CP is LOW and transfers to
the slave when CP goes HIGH. When the CEN input goes
HIGH it overrides all other inputs, disables the clock, and
the Q outputs maintain the last state.
The 100353 output drivers are designed to drive 50Ω termi-
nation to −2.0V. All inputs have 50 kΩ pull-down resistors.
Features
a73 Low power operation
a73 2000V ESD protection
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Available to industrial grade temperature range

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
100353PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100353QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100353QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
D
0
–D
7
Data Inputs
CEN Clock Enable Input
CP Clock Input (Active Rising Edge)
Q
0
–Q
7
Data Outputs
NC No Connect