© 2000 Fairchild Semiconductor Corporation DS009885 www.fairchildsemi.com
July 1988
Revised August 2000
1
00351 Low
Power Hex
D-
T
y
pe
Fl
i
p
-Fl
o
p
100351
Low Power Hex D-Type Flip-Flop
General Description
The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and complement outputs, a pair of
common Clock inputs (CP
a
and CP
b
) and common Master
Reset (MR) input. Data enters a master when both CP
a
and CP
b
are LOW and transfers to the slave when CP
a
and
CP
b
(or both) go HIGH. The MR input overrides all other
inputs and makes the Q outputs LOW. All inputs have
50 kΩ pull-down resistors.
Features
a73 40% power reduction of the 100151
a73 2000V ESD protection
a73 Pin/function compatible with 100151
a73 Voltage compensated operating range:
−4.2V to −5.7V
a73 Available to industrial grade temperature range

Ordering Code:
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
D
0
–D
5
Data Inputs
CP
a
, CP
b
Common Clock Inputs
MR Asynchronous Master Reset Input
Q
0
–Q
5
Data Outputs
Q
0
–Q
5
Complementary Data Outputs