© 2000 Fairchild Semiconductor Corporation DS009884 www.fairchildsemi.com
July 1988
Revised August 2000
1
00350 Low
Power Hex
D-
T
y
pe
La
tch
100350
Low Power Hex D-Type Latch
General Description
The 100350 contains six D-type latches with true and com-
plement outputs, a pair of common Enables (E
a
and E
b
),
and a common Master Reset (MR). A Q output follows its D
input when both E
a
and E
b
are LOW. When either E
a
or E
b
(or both) are HIGH, a latch stores the last valid data
present on its D input before E
a
or E
b
went HIGH. The MR
input overrides all other inputs and makes the Q outputs
LOW. All inputs have 50 kΩ pull-down resistors.
Features
a73 20% power reduction of the 100150
a73 2000V ESD protection
a73 Pin/function compatible with 100150
a73 Voltage compensated operating range = −4.2V to −5.7V

Ordering Code:
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
100350PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100350QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Pin Names Description
D
0
–D
5
Data Inputs
E
a
, E
b
Common Enable Inputs (Active LOW)
MR Asynchronous Master Reset Input
Q
0
–Q
5
Data Outputs
Q
0
–Q
5
Complementary Data Outputs