100344
Low Power 8-Bit Latch with Cut-Off Drivers
General Description
The 100344 contains eight D-type latches, individual inputs
(D
n
), outputs (Q
n
), a common enable pin (E), latch enable
(LE), and output enable pin (OEN). A Q output follows its D
input when both E and LE are LOW. When either E or LE (or
both) are HIGH, a latch stores the last valid data present on
its D input prior to E or LE going HIGH.
A HIGH on OEN holds the outputs in a cut-off state. The
cut-off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is −2.0V, presenting a
high impedance to the data bus. This high impedance re-
duces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100344 outputs are designed to drive a doubly termi-
nated 50Ω transmission line (25Ω load impedance). All in-
puts have 50 kΩ pull-down resistors.
Features
n Cut-off drivers
n Drives 25Ω load
n Low power operation
n 2000V ESD protection
n Voltage compensated operating range = −4.2V to −5.7V
n Available to MIL-STD-883
Logic Symbol
Pin Names Description
D
0
–D
7
Data Inputs
E Enable Input
LE Latch Enable Input
OEN Output Enable Input
Q
0
–Q
7
Data Outputs
Connection Diagrams
DS100317-4
24-Pin DIP
DS100317-1
24-Pin Quad Cerpak
DS100317-2
August 1998
100344
Low
Power
8-Bit
Latch
with
Cut-Off
Drivers
© 1998 National Semiconductor Corporation DS100317 www.national.com