100341QC
器件描述：Low Power 8-Bit Shift Register
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：94.96KB，共9页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS009880 www.fairchildsemi.com
July 1988
Revised August 2000
1
00341 Low
Power 8-Bi
t Shif
t Regi
ster
100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (P
n
) and outputs (Q
n
) for parallel
operation, and with serial inputs (D
n
) and steering logic for
bidirectional shifting. The flip-flops accept input data a
setup time before the positive-going transition of the clock
pulse and their outputs respond a propagation delay after
this rising clock edge.
The circuit operating mode is determined by the Select
inputs S
0
and S
1
, which are internally decoded to select
either “parallel entry”, “hold”, “shift left” or “shift right” as
described in the Truth Table. All inputs have 50 kΩ pull-
down resistors.
Features
a73 35% power reduction of the 100141
a73 2000V ESD protection
a73 Pin/function compatible with 100141
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Available to industrial grade temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
10034SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100341PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100341QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100341QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
CP Clock Input
S
0
, S
1
Select Inputs
D
0
, D
7
Serial Inputs
P
0
–P
7
Parallel Inputs
Q
0
–Q
7
Data Outputs
July 1988
Revised August 2000
1
00341 Low
Power 8-Bi
t Shif
t Regi
ster
100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (P
n
) and outputs (Q
n
) for parallel
operation, and with serial inputs (D
n
) and steering logic for
bidirectional shifting. The flip-flops accept input data a
setup time before the positive-going transition of the clock
pulse and their outputs respond a propagation delay after
this rising clock edge.
The circuit operating mode is determined by the Select
inputs S
0
and S
1
, which are internally decoded to select
either “parallel entry”, “hold”, “shift left” or “shift right” as
described in the Truth Table. All inputs have 50 kΩ pull-
down resistors.
Features
a73 35% power reduction of the 100141
a73 2000V ESD protection
a73 Pin/function compatible with 100141
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Available to industrial grade temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
10034SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100341PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100341QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100341QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
CP Clock Input
S
0
, S
1
Select Inputs
D
0
, D
7
Serial Inputs
P
0
–P
7
Parallel Inputs
Q
0
–Q
7
Data Outputs