© 2000 Fairchild Semiconductor Corporation DS010262 www.fairchildsemi.com
February 1990
Revised August 2000
1
00331 Low
Power T
r
i
p
le D-T
y
pe

Fl
ip-
F
lop
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
C
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
),
Direct Set (SD
n
) and Direct Clear (CD
n
) inputs. Data enters
a master when both CP
n
and CP
C
are LOW and transfers
to a slave when CP
n
or CP
C
(or both) go HIGH. The Master
Set, Master Reset and individual CD
n
and SD
n
inputs over-
ride the Clock inputs. All inputs have 50 kΩ pull-down
resistors.
Features
a73 35% power reduction of the 100131
a73 2000V ESD protection
a73 Pin/function compatible with 100131
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Available to industrial grade temperature range

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Order Number Package Number Package Description
100331SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
CP
0
–CP
2
Individual Clock Inputs
CP
C
Common Clock Input
D
0
–D
2
Data Inputs
CD
0
–CD
2
Individual Direct Clear Inputs
SD
n
Individual Direct Set Inputs
MR Master Reset Input
MS Master Set Input
Q
0
-Q
2
Data Outputs
Q
0
–Q
2
Complementary Data Outputs