100329A
器件描述：Low Power Octal ECL/TTL Bidirectional Translator with Register
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：88.18KB，共8页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS500047 www.fairchildsemi.com
August 1989
Revised August 2000
1
00329A L
o
w
Power
O
c
tal
ECL/
TTL Bi
dir
ect
ional
T
r
ansl
ator
wi
th
Regist
er
100329A
Low Power Octal ECL/TTL Bidirectional Translator with
Register
General Description
The 100329A is an octal registered bidirectional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of the translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. The outputs change
synchronously with the rising edge of the clock input (CP)
even though only one output is enabled at the time.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces the termination power and prevents
loss of low state noise margin when several loads share
the bus.
The 100329A is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 kΩ pull-down resistors.
Features
a73 Bidirectional translation
a73 ECL high impedance outputs
a73 Registered outputs
a73 FAST TTL outputs
a73 3-STATE outputs
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 High drive IOS
Ordering Code:
Logic Symbol
Pin Descriptions
All pins function at 100K ECL levels except for T
0
–T
7
.
Connection Diagram
FAST is a registered trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
100329APC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Pin Names Description
E
0
–E
7
ECL Data I/O
T
0
–T
7
TTL Data I/O
OE Output Enable Input
CP Clock Pulse Input
(Active Rising Edge)
DIR Direction Control Input
August 1989
Revised August 2000
1
00329A L
o
w
Power
O
c
tal
ECL/
TTL Bi
dir
ect
ional
T
r
ansl
ator
wi
th
Regist
er
100329A
Low Power Octal ECL/TTL Bidirectional Translator with
Register
General Description
The 100329A is an octal registered bidirectional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of the translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. The outputs change
synchronously with the rising edge of the clock input (CP)
even though only one output is enabled at the time.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces the termination power and prevents
loss of low state noise margin when several loads share
the bus.
The 100329A is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 kΩ pull-down resistors.
Features
a73 Bidirectional translation
a73 ECL high impedance outputs
a73 Registered outputs
a73 FAST TTL outputs
a73 3-STATE outputs
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 High drive IOS
Ordering Code:
Logic Symbol
Pin Descriptions
All pins function at 100K ECL levels except for T
0
–T
7
.
Connection Diagram
FAST is a registered trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
100329APC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Pin Names Description
E
0
–E
7
ECL Data I/O
T
0
–T
7
TTL Data I/O
OE Output Enable Input
CP Clock Pulse Input
(Active Rising Edge)
DIR Direction Control Input