100323
器件描述：Low Power Hex Bus Driver
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：67.03KB，共6页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS009877 www.fairchildsemi.com
July 1988
Revised August 2000
1
00323 Low
Power Hex
Bus Dri
ver
100323
Low Power Hex Bus Driver
General Description
The 100323 is a monolithic device containing six bus driv-
ers capable of driving terminated lines with terminations as
low as 25Ω. To reduce crosstalk, each output has its own
respective ground connection. Transition times were
designed to be longer than on other F100K devices. The
driver itself performs the positive logic AND of a data input
(D
1
–D
6
) and the OR of two select inputs (E and either DE
1
,
DE
2
, or DE
3
).
Enabling of data is possible in multiples of two, i.e., 2, 4 or
all 6 paths. All inputs have 50 kΩ pull-down resistors.
The output voltage LOW level is designed to be more neg-
ative than normal ECL outputs (cut off state). This allows
an emitter-follower output transistor to turn OFF when the
termination supply is −2.0V and thus present a high imped-
ance to the data bus.
Features
a73 50% power reduction of the 100123
a73 2000V ESD protection
a73 −4.2V to −5.7V operating range
a73 Drives 25Ω load
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
100323PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100323QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Pin Names Description
D
1
–D
6
Data Inputs
DE
1
–DE
3
Dual Enable Inputs
E Common Enable Input
O
1
–O
6
Data Outputs
July 1988
Revised August 2000
1
00323 Low
Power Hex
Bus Dri
ver
100323
Low Power Hex Bus Driver
General Description
The 100323 is a monolithic device containing six bus driv-
ers capable of driving terminated lines with terminations as
low as 25Ω. To reduce crosstalk, each output has its own
respective ground connection. Transition times were
designed to be longer than on other F100K devices. The
driver itself performs the positive logic AND of a data input
(D
1
–D
6
) and the OR of two select inputs (E and either DE
1
,
DE
2
, or DE
3
).
Enabling of data is possible in multiples of two, i.e., 2, 4 or
all 6 paths. All inputs have 50 kΩ pull-down resistors.
The output voltage LOW level is designed to be more neg-
ative than normal ECL outputs (cut off state). This allows
an emitter-follower output transistor to turn OFF when the
termination supply is −2.0V and thus present a high imped-
ance to the data bus.
Features
a73 50% power reduction of the 100123
a73 2000V ESD protection
a73 −4.2V to −5.7V operating range
a73 Drives 25Ω load
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
100323PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100323QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Pin Names Description
D
1
–D
6
Data Inputs
DE
1
–DE
3
Dual Enable Inputs
E Common Enable Input
O
1
–O
6
Data Outputs