100302
器件描述:Low Power Quint 2-Input OR/NOR Gate
文件大小:78.62KB,共8页
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器件资料摘要:
© 2000 Fairchild Semiconductor Corporation DS010580 www.fairchildsemi.com
August 1989
Revised August 2000
1
00302 Low
Power Quint
2-
Inp
u
t O
R
/
N
OR
Gate
100302
Low Power Quint 2-Input OR/NOR Gate
General Description
The 100302 is a monolithic quint 2-input OR/NOR gate with
common enable. All inputs have 50 kΩ pull-down resistors
and all outputs are buffered.
Features
a73 43% power reduction of the 100102
a73 2000V ESD protection
a73 Pin/function compatible with 100102
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC 28-Pin PLCC
Pin Descriptions
Order Number Package Number Package Description
100302SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100302PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100302QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100302QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
D
na
–D
ne
Data Inputs
E Enable Input
O
a
–O
e
Data Outputs
O
a
–O
e
Complementary Data Outputs