© 2000 Fairchild Semiconductor Corporation DS010582 www.fairchildsemi.com
August 1989
Revised August 2000
1
00307 Low
Power Quint

Excl
usi
ve
OR/
N
OR G
a
te
100307
Low Power Quint Exclusive OR/NOR Gate
General Description
The 100307 is monolithic quint exclusive-OR/NOR gate.
The Function output is the wire-OR of all five exclusive-OR
outputs. All inputs have 50 kΩ pull-down resistors.
Features
a73 Low Power Operation
a73 2000V ESD protection
a73 Pin/function compatible with 100107
a73 Voltage compensated operating range = −4.2V to −5.7V
a73 Available to industrial grade temperature range
(PLCC package only)

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Logic Equation
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number Package Number Package Description
1000307PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
1000307QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
1000307QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Pin Names Description
D
na
–D
ne
Data Inputs
F Function Output
O
a
–O
e
Data Outputs
O
a
–O
e
Complementary
Data Outputs
F = (D
1a
⊕ D
2a
) + (D
1b
⊕ D
2b
) + (D
1c
⊕ D
2c
) +
(D
1d
⊕ D
2d
) + (D
1e
⊕ D
2e
).