May 2001
Copyright ©Alliance Semiconductor. All rights reserved.
®
AS4LC2M8S1
AS4LC2M8S0
AS4LC1M16S1
AS4LC1M16S0
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM
5/21/01; v.1.1 Alliance Semiconductor P. 1 of 29
Preliminary
• Auto refresh and self refresh
PC100 functionality
Automatic and direct precharge including concurrent
autoprecharge
Burst read, write/Single write
Random column address assertion in every cycle, pipelined
operation
LVTTL compatible I/O
3.3V power supply
JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP 2 (2M × 8)
- 400 mil, 50-pin TSOP 2 (1M × 16)
Read/write data masking
Programmable burst length (1/2/4/8/ full page)
Programmable burst sequence (sequential/interleaved)
Programmable CAS latency (1/2/3)
Selection guide
Symbol –7 –8 –10 Unit
Bus frequency (CL = 3) f
Max
143 125 100 MHz
Maximum clock access time (CL = 3) t
AC
5.5 6 6 ns
Minimum input setup time t
S
222
Minimum input hold time t
H
1.0 1.0 1.0 ns
Row cycle time (CL = 3, BL = 1) t
RC
70 80 80 ns
Maximum operating current ([×16], RD or
WR, CL = 3), BL = 2
I
CC1
130 100 100 mA
Maximum CMOS standby current, self refresh I
CC6
11
Pin designation
Pin(s) Description
DQM (2M × 8)
UDQM/LDQM (1M × 16)
Output disable/write mask
A0 to A10 Address inputs
RA0 – 10
CA0 – 7 (×16)
CA0 – 8 (×8)
A11 Bank address (BA)
DQ0 to DQ7 (2M × 8)
DQ0 to DQ15 (1M × 16)
Input/output
RAS Row address strobe
CAS Column address strobe
WE Write enable
CS Chip select
V
CC
, V
CCQ
Power (3.3V ± 0.3V)
V
SS
, V
SSQ
Ground
CLK Clock input
CKE Clock enable
Pin arrangement
V
CC
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
CCQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
CCQ
LDQM
WE
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
CCQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
CCQ
NC
UDQM
CLK
CKE
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TSOP 2
AS4LC1M16S
0
23
24
25
28
27
26
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
V
SSQ
DQ1
V
CCQ
DQ2
V
SSQ
DQ3
V
CCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
V
SSQ
DQ6
V
CCQ
DQ5
V
SSQ
DQ4
V
CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TSOP 2
AS4LC2
M8S0
AS
4LC2M8S1
and
and
AS4LC1M16S
1
Features
Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
11 row, 9 column address
- 524,288 words × 16 bits × 2 banks (1M × 16)
11 row, 8 column address
All signals referenced to positive edge of clock, fully
synchronous
Dual internal banks controlled by A11 (bank select)
High speed
- 143/125/100 MHz
- 7/8/10 ns clock access time
Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
2048 refresh cycles, 32 ms refresh interval
4096 refresh cycles, 64 ms refresh interval
LEGEND 2M × 81M × 16
Configuration 1M × 8 × 2 banks 512K × 16 × 2 banks
Refresh Count 2K/4K 2K/4K
Row Address (A0 – A10) (A0 – A10)
Bank Address 2 (BA) 2 (BA)
Column Address 512 (A0 – A8) 256 (A0 – A7)