The wireless communication solution provider
AR2010
The AR2010 GPS controller SoC is a single chip integrated processor with
peripherals suitable for all GPS receiver related products, GPS engine board,
GPS mouse, GPS CF-card, GPS watch, GPS handheld navigator/locator, PDA
with GPS receiver, add-on notebook PC and other specific designs.
GPS Controller SoC
Ar2010 Block Diagram
FEATURES:
The AR2010 controller SoC includes the following functions and capabilities:
CPU: MIPS 1 class R3000 level, 32-bit RISC processor with 2 KB
Instruction cache and 2 KB data cache, and up to 100 MHz CPU
Clock rate
Built-in 64 KB SRAM
SDRAM Controller supports two SDRAM banks of 16-bit data bus
Up to 32 MB address space
GPS Base-band decoder with 12 channel correlators and built-in
carrier/code tracking loops
LCD display interface driver
ADC with touch screen interface controller
Supports GPIOs for multi-purpose peripherals
2 UART channels for serial communications
Real time clock with alarm
Async SRAM/
Mask ROM/
Flash ROM
GPS
Decoder
RTC/
Timer
UART
x2
MIPS-R3000
1 class CPU
with 2K/2K
I/D cache
SDRAM
Ctlr
EJTAG
DSU
SDRAM
LCD Ctlr
(20KB/FB)
Touch
Panel Ctlr
PLL&P
Custom
Devices
LCD Panel
&
Touch
Panel
Key Pad/
LED
GPS RF
Front-end
IrDA Devices
Rs232
Drivers
Battery