PRODUCT PREVIEW
FEATURES
APPLICATIONS
DESCRIPTION
10−Bit
ADC
PLL
S/H Serializer
1X ADCLK
6X ADCLK
IN1P
ADCLK
IN1N
OUT1P
OUT1N
10−Bit
ADCS/H Serializer
IN2P
IN2N
OUT2P
OUT2N
10−Bit
ADCS/H Serializer
IN3P
IN3N
OUT3P
OUT3N
LCLKP
LCLKN
ADCLKP
ADCLKN
10−Bit
ADCS/H Serializer
IN4P
IN4N
OUT4P
OUT4N
10−Bit
ADCS/H Serializer
IN5P
IN5N
OUT5P
OUT5N
10−Bit
ADCS/H Serializer
IN6P
IN6N
OUT6P
OUT6N
10−Bit
ADCS/H Serializer
IN7P
IN7N
OUT7P
OUT7N
10−Bit
ADCS/H Serializer
Reference
IN8P
IN8N
R
E
F
TINT/EXT
V
C
M
R
E
F
B
OUT8P
OUT8N
Registers
S
C
L
K
S
D
A
T
A
C
S
Control
R
E
S
E
T
P
D
ADS5275
SBAS300 – JANUARY 2004 – REVISED NOVEMBER 2004
8-Channel, 10-Bit, 40MSPS ADC
with Serial LVDS Interface
The ADS5275 provides internal references, or can
optionally be driven with external references. Best• Maximum Sample Rate: 40MSPS
performance can be achieved through the internal• 10-Bit Resolution
reference mode.
• No Missing Codes The ADS5275 is available in a PowerPAD TQFP-80
• Power Dissipation: 768mW package and are specified over a -40 ° C to +85 ° C
operating range.• CMOS Technology
• Simultaneous Sample-and-Hold
• 60.5dB SNR at 10MHz IF
• Serialized LVDS Outputs Meet or Exceed
Requirements of ANSI TIA/EIA-644-A Standard
• Internal and External References
• 3.3V Digital/Analog Supply
• TQFP-80 PowerPAD ™ Package
• Portable Ultrasound Systems
• Tape Drives
• Test Equipment
The ADS5275 is a high-performance, 40MSPS,
8-channel, parallel analog-to-digital converter (ADC).
Internal references are provided, simplifying system
design requirements. Low power consumption allows
for the highest of system integration densities. Serial
LVDS (low-voltage differential signaling) outputs re-
duce the number of interface lines and package size.
In LVDS, an integrated phase lock loop multiplies the
incoming ADC sampling clock by a factor of 6. This
high-frequency LVDS clock is used in the data
serialization and transmission process and is con-
verted to an LVDS signal for transmission in parallel
with the data. Providing this additional LVDS clock
allows for easy delay matching. The word output of
each internal ADC is serialized and transmitted either
MSB or LSB first. The bit following the rising edge of
the ADC clock output is the first bit of the word.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the forma- Copyright © 2004, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.