74LVT16245GX
器件描述：Low Voltage 16-Bit Transceiver with 3-STATE Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：76.1KB，共8页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS500152 www.fairchildsemi.com
January 1999
Revised June 2005
7
4
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• 74L
VTH16245 Low
V
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74LVT16245 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH16245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT16245
and LVTH16245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
a73 Input and output interface capability to systems at
5V V
CC
a73 Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16245),
also available without bushold feature (74LVT16245).
a73 Live insertion/extraction permitted
a73 Power Up/Down high impedance provides glitch-free
bus loading
a73 Outputs source/sink c1632 mA/c1464 mA
a73 Functionally compatible with the 74 series 16245
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human-body model c332000V
Machine model c33200V
Charged-device c331000V
a73 Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package
Number
Package Description
74LVT16245GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVT16245MEA
(Note 2)
MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16245MTD
(Note 2)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16245GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVTH16245MEA
(Note 2)
MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16245MTD
(Note 2)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
January 1999
Revised June 2005
7
4
L
V
T1
6245
• 74L
VTH16245 Low
V
o
l
t
age 16-Bi
t T
r
ansc
eiver
wi
th 3-ST
A
T
E
Out
put
s
74LVT16245 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH16245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT16245
and LVTH16245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
a73 Input and output interface capability to systems at
5V V
CC
a73 Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16245),
also available without bushold feature (74LVT16245).
a73 Live insertion/extraction permitted
a73 Power Up/Down high impedance provides glitch-free
bus loading
a73 Outputs source/sink c1632 mA/c1464 mA
a73 Functionally compatible with the 74 series 16245
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human-body model c332000V
Machine model c33200V
Charged-device c331000V
a73 Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package
Number
Package Description
74LVT16245GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVT16245MEA
(Note 2)
MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16245MTD
(Note 2)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16245GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVTH16245MEA
(Note 2)
MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16245MTD
(Note 2)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide