BCRT-1
UT1553B BC RT
FEATURES
p Comprehensive MIL-STD-1553B dual-redundant
Bus Controller (BC) and Remote Terminal
(RT) functions
p MIL-STD-1773 compatible
p Multiple message processing capability in BC and
RT modes
p Time-tagging and message logging in RT mode
p Automatic polling and intermessage delay in
BC mode
p Programmable interrupt scheme and internally
generated interrupt history list
p Register-oriented architecture to enhance
programmability
p DMA memory interface with 64K addressability
p Internal self-test
p Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p The UT1553B BCRT is not available radiation-harden
ed
p Packaged in 84-pin pingrid array, 84- and 132-lead
flatpack, 84-lead leadless chip carrier packages
p Standard Microcircuit Drawing 5962-88628 available
- QML Q and V compliant
16
16
16
HANDLERINTERRUPT
BUS
TRANSFER
LOGIC
ADDRESS
16TIMEOUT
CLOCK &
RESET
12MHZ
MASTER
RESET
GENERATOR
ADDRESS
16
1553
HIGH-PRIORITY
RT ADDRESS
STANDARD INTERRUPT
HIGH-PRIORITY
INTERRUPT LOG
CURRENT COMMAND
BUILT-IN-TEST WORD
POLLING COMPARE
CURRENT BC BLOCK/
STATUS
CONTROL
REGISTERS
LIST POINTER
DATA
16
BUILT-
IN-
TEST
16
16
RT TIMER TAG
INTERRUPT STATUS/RESET
INTERRUPT ENABLEDATA
CHANNEL
B
1553
DATA
CHANNEL
A
LOGIC
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
RT DESCRIPTOR SPACE
ENABLE
BUILT-IN-TEST
START COMMAND
PROGRAMMED RESET
RESET COMMAND
TIMERON
SERIAL to
PARALLEL-
CONVER-
SION
PARALLEL-
TO-SERIAL
CONVER-
SION
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
RT PROTOCOL
& MESSAGE
HANDLER
DMA/CPU
CONTROL
BC PROTOCOL
& MESSAGE
HANDLER
Figure 1. BCRT Block Diagram