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厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

5211AI03

器件描述:LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
器件厂商:ICST [Integrated Circuit Systems]
厂商主页:http://www.icst.com
文件大小:107.99KB,共13页
Sponsor by e络盟
器件资料摘要:
85211AMI-03 www.icst.com/products/hiperclocks.html REV. B APRIL 8, 2003
1
G73G110G116G101G103G114G97G116G101G100
G67G105G114G99G117G105G116
G83G121G115G116G101G109G115G44G32G73G110G99G46._
ICS85211I-03
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
BLOCK DIAGRAM PIN ASSIGNMENT
GENERAL DESCRIPTION
The ICS85211I-03 is a low skew, high perfor-
mance 1-to-2 Differential-to-LVHSTL Fanout
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels.The ICS85211I-03 is char-
acterized to operate from a 3.3V power supply. Guar-
anteed output and part-to-part skew characteristics
make the ICS85211I-03 ideal for those clock distribution
applications demanding well defined performance and
repeatability. For optimal performance, terminate all outputs.
FEATURES
• 2 differential LVHSTL compatible outputs
• 1 differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to
LVHSTL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1ns (maximum)
• Output duty cycle: 49% - 51% up to 266.6MHz
• V
OH
= 1V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
HiPerClockS™
c44c38c54
ICS85211I-03
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
VDD
CLK
nCLK
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK