Se
*
Pe
the
lection guide
AS7C33256PFS16A
–166
AS7C33
–15
Minimum cycle time 6
Maximum pipelined clock frequency 166 1
Maximum pipelined clock access time 3.5
Maximum operating current 475 4
3/14/01; V.1.0 Alliance Semicondu
ntium
®
is a registered trademark of Intel Corporation. NTD™ is a trademark of Allian
property of their respective owners.
Maximum standby current 130
Maximum CMOS standby current (DC) 30
256PFS16A
0
AS7C33256PFS16A
–133
AS7C33256PFS16A
–100 Units
6.7 7.5 10 ns
50 133 100 MHz
3.8 4 5 ns
50 425 325 mA
Note: pins 24, 74 are NC for ×16.
Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD16A/
AS7C33256PFD18A)

N
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
181618
A[17:0]
18
Address
D Q
CS
CLK
register
256K × 16/18
Memory
array
16/18
16/18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DATA [17:0]
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
FT
CLK
CLK
DATA [15:0]
BWE
GWE
Pin ar
DDQ
30 mW typical standby power in power down mode
TD™
*
pipeline architecture available
(AS7C33256NTD16A/AS7C33256NTD18A)
rangement
LBO
A5 A4 A3 A2 A1 A0
NC NC V
SS
V
DD
NC NC
A10 A11 A12 A13 A14 A15
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A6 A7 CE0 CE1 NC NC BW
b
BW
a
CE2 V
DD

V
SS
CLK GWE BW
E
OE AD
S
C
AD
S
P
AD
V
A8 A9
A16
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
V
DD
TQFP 14 × 20mm
March 2001
AS7C33256PFS16A
AS7C33256PFS18A
3.3V 256K × 16/18 pipeline burst synchronous SRAM
®
Features
• Organization: 262,144 words × 16 or 18 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4.0/5.0 ns
Fast OE access time: 3.5/3.8/4.0/5.0 ns
Fully synchronous register-to-register operation
“Flow-through” mode
Pentium®
*
compatible architecture and timing
Asynchronous output enable control
Economical 100-pin TQFP package
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
Copyright © Alliance Semiconductor. All rights reserved.
ctor P. 1 of 11
ce Semiconductor Corporation. All trademarks mentioned in this document are
110 100 90 mA
30 30 30 mA