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SCES589B − AUGUST 2004 − REVISED APRIL 2005
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C0068 Member of the Texas Instruments
Widebus+ Family
C0068 Control Inputs V
IH
/V
IL
Levels Are
Referenced to V
CCA
Voltage
C0068 V
CC
Isolation Feature − If Either V
CC
Input
Is at GND, Both Ports Are in the
High-Impedance State
C0068 Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
C0068 Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
C0068 I
off
Supports Partial-Power-Down Mode
Operation
C0068 I/Os Are 4.6-V Tolerant
C0068 Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
C0068 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
C0068 ESD Protection Exceeds JESD 22
− 8000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVCH32T245 is optimized to operate with V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as low as 1.2 V. The A port is designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The
B port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH32T245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCH32T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 1OE, 2OE, 3OE, and
4OE) are supplied by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both ports are in the high-impedance
state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
LFBGA − GKE
Tape and reel
SN74AVCH32T245KR
WJ245
LFBGA − ZKE (Pb-free)
ape and reel
74AVCH32T245ZKER
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright  2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
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