FEATURES
APPLICATIONS
DESCRIPTION
12−Bit
ADC
PLL
S/H Serializer
1x ADCLK
6x ADCLK
IN1P
ADCLK
IN1N
OUT1P
OUT1N
12−Bit
ADCS/H Serializer
IN2P
IN2N
OUT2P
OUT2N
12−Bit
ADCS/H Serializer
IN3P
IN3N
OUT3P
OUT3N
LCLKP
LCLKN
ADCLKP
ADCLKN
12x ADCLK
12−Bit
ADCS/H Serializer
IN4P
IN4N
OUT4P
OUT4N
Reference
R
E
F
TINT/EXT
V
C
M
R
E
F
B
Registers
S
C
L
K
S
D
A
T
A
C
S
Control
R
E
S
E
T
P
D
ADS5242
SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005
4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter
with Serial LVDS Interface
An integrated phase lock loop (PLL) multiplies the
incoming ADC sampling clock by a factor of 12. This• Maximum Sample Rate: 65MSPS
high-frequency LVDS clock is used in the data• 12-Bit Resolution
serialization and transmission process. The word
output of each internal ADC is serialized and• No Missing Codes
transmitted either MSB or LSB first. In addition to the• Total Power Dissipation
four data outputs, a bit clock and a word clock areInternal Reference: 660mW
also transmitted. The bit clock is at 6x the speed ofExternal Reference: 594mW
the sampling clock, whereas the word clock is at the• CMOS Technology
same speed of the sampling clock.
• Simultaneous Sample-and-Hold The ADS5242 provides internal references, or can
• 70.8dBFS SNR at 10MHz IF optionally be driven with external references. Best
performance can be achieved through the internal• 3.3V Digital/Analog Supply
reference mode.• Serialized LVDS Outputs
The device is available in an HTQFP-64 PowerPAD• Integrated Frame and Bit Patterns
package and is specified over a – 40 ° C to +85 ° C• Option to Double LVDS Clock Output Currents
operating range.
• Four Current Modes for LVDS
• Pin- and Format-Compatible Family
• HTQFP-64 PowerPAD ™ Package
• Portable Ultrasound Systems
• Tape Drives
• Test Equipment
• Optical Networking
• Communications
The ADS5242 is a high-performance, 65MSPS,
4-channel analog-to-digital converter (ADC). Internal
references are provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
(low-voltage differential signaling) outputs reduce the
number of interface lines and package size.
RELATED PRODUCTS
RESOLUTION SAMPLE RATE
MODEL (BITS) (MSPS) CHANNELS
ADS5240 12 40 4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004 – 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.