10-Bit, 65/80/105 MSPS
Dual A/D Converter
Preliminary Technical Data AD9216


Rev. PrD_6/15/2004
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FEATURES
Integrated Dual 10-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist, AD9216-105)
SFDR = 75 dBc (to Nyquist, AD9216-105)
Low Power: 280mW at 105MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 75dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
3G, Radio Point-to-Point, LMDS, MMDS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 65/80/105 MSPS analog-to-
digital converter. It features dual high performance sample-and
hold amplifiers and an integrated voltage reference. The
AD9216 uses a multistage differential pipelined architecture
with output error correction logic to provide 10-bit accuracy
and guarantee no missing codes over the full operating
temperature range at up to 105 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well
beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9216 (all speed grades) and can compensate for wide
variations in the clock duty cycle, allowing the converters to
maintain excellent performance. The digital output data is
presented in either straight binary or twos complement format.
Out-of-range signals indicate an overflow condition, which can
be used with the most significant bit to determine low or high
overflow.
Fabricated on an advanced CMOS process, the AD9216 is
available in a space saving 64-lead LFCSP (9x9) and is
specified over the industrial temperature range (–40°C to
+85°C).
ADC D9A-D0A
Output Mux/
Buffers
AGND
VIN- _A
CLK_A
AD9216
SHA 10VIN+_A
DCSSENSE
REFT_A
10
AVDD
ADCVIN-_B SHAVIN+_B 10 D10B-D0B10
MUX_SELECT
CLK_B
AGND
DRGND
SHARED_REF
PWDN_A
DFS
Mode
Control
+-
REFB_A
REFT_B
REFB_B
Clock
Duty Cycle
Stabilizer
PWDN_B
OTR_B
OEB_B
OEB_A
OTR_A
Output Mux/
Buffers
0.5V
VREF
DRVDD
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
1. Pin compatible with AD9238, dual 12-bit
20/40/65MSPS ADC and AD9248, dual 14-bit
20/40/65MSPS ADC.
2. Speed grade options off 105 MSPS, 80 MSPS, and
65 MSPS allow flexibility between power, cost, and
performance to suit an application.
3. Low power consumption:
AD9216-105: 105 MSPS = 280 mW
AD9216-80: 80 MSPS = 238 mW
AD9216-65: 65 MSPS = 215mW
4. The patented SHA input maintains excellent
performance for input frequencies up to 100 MHz and
can be configured for single-ended or differential
operation.
5. Typical channel isolation of 75 dB @ fIN = 10 MHz.
6. The clock duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.