2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
B9940L
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07105 Rev. *C Revised December 26, 2002
Features
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 150-ps max. output-to-output skew
• Dual- or single-supply operation:
— 3.3V core and 3.3V outputs
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
• Pin-compatible with MPC940L
• Industrial temperature range: -40°C to 85°C
• 32-pin LQFP package
Description
The B9940L is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL- or an
LVCMOS/LVTTL-compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are
LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V compatible and can drive two series-terminated 50Ω
transmission lines. With this capability the B9940L has an
effective fan-out of 1:36. Low output-to-output skews make the
B9940L an ideal clock distribution buffer for nested clock trees
in the most demanding of synchronous systems.
Block Diagram
Pin Configuration
B9940L
Q0 Q1 Q2 VD
D
C
Q3 Q4 Q5 VS
S
Q1
7
Q1
6
Q1
5
VSS Q1
4
Q1
3
Q1
2
VD
D
C
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
PECL_CLK
PECL_CLK#
0
1TCLK
TCLK_SEL
VDDC
18
Q0-Q17
VDD