SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
AS4SD4M16
Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
• Extended Testing Over -55°C to +125° C and
Industrial Temp -40°C to 85° C
• WRITE Recovery ( t
WR
/ t
DPL
) t
WR
= 2 CLK
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode (Industrial, -40°C to 85° C only)
• 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability
(OCPL*)
• Short Flow / Long Flow Test Screening Options
OPTIONS MARKING
• Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16
• Plastic Package - OCPL*
54-pin TSOP (400 mil) DG No. 901
• Timing (Cycle Time)
8ns; t
AC
= 6.5ns @ CL = 3 ( t
RP
- 24ns) -8
10ns; t
AC
= 9ns @ CL = 2 -10
• Operating Temperature Ranges
-Military (-55°C to +125° C) XT
-Industrial Temp (-40°C to 85° C) IT
KEY TIMING PARAMETERS
SPEED CLOCK SETUP HOLD
GRADE FREQUENCY CL = 2** CL = 3** TIME TIME
-8 125 MHz – 6.5ns 2ns 1ns
-10 100 MHz – 7ns 3ns 1ns
-8 83 MHz 9ns – 2ns 1ns
-10 66 MHz 9ns – 3ns 1ns
ACCESS TIME
*Off-center parting line
**CL = CAS (READ) latency
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
Note: “\” indicates an active low.
Configuration 1 Meg x 16 x 4 banks
Refresh Count 4K
Row Addressing 4K (A0-A11)
Bank Addressing 4 (BA0, BA1)
Column Addressing 256 (A0-A7)
4 Meg x 16
4 Meg x 16 SDRAM
Synchronous DRAM Memory
For more products and information
please visit our web site at
www.austinsemiconductor.com