1/11April 2001
a73 HIGH SPEED: t
PD
= 4.5ns (TYP.) at V
CC
= 5V
a73 LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
a73 HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
a73 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL

a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched at the logic level of D input data. While the
(OE) input is low, the 8 outputs will be in a normal
logic state (high or low logic level); while OE is in
high level, the outputs will be in a high impedance
state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)

PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
DIP 74AC573B
SOP 74AC573M 74AC573MTR
TSSOP 74AC573TTR
TSSOPDIP SOP