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1OEAB
1OEBA
VCC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
VCC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
VCC
2A8
GND
2OEAB
2OEBA
CLK
1LEAB
1LEBA
ERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
VCC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
VREF
2B6
GND
2B7
2B8
BIAS VCC
2LEAB
2LEBA
OE
DESCRIPTION
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C – OCTOBER 1999 – REVISED MAY 2005
• Member of Texas Instruments' Widebus ™
Family
• UBT ™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
• TI-OPC ™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
• OEC ™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
• Partitioned as Two 8-Bit Transceivers With
Individual Latch Timing and Output Control,
but With a Common Clock
• LVTTL Interfaces Are 5-V Tolerant
• High-Drive GTLP Outputs (100 mA)
• LVTTL Outputs ( – 24 mA/24 mA)
• Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
• I off , Power-Up 3-State, and BIAS V CC Support
Live Insertion
• Bus Hold on A-Port Data Inputs
• Distributed V CC and GND Pins Minimize
High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The SN74GTLPH1655 is a high-drive, 16-bit UBT ™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent,
latched, and clocked modes of data transfer. The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing
( <1 V), reduced input threshold levels, improved differential input, OEC ™ circuitry, and TI-OPC ™ circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 11 Ω .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 1999 – 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.