Industrial and commercial temperature ranges available
Organization: 262,144 words × 16 bits
2.7V to 3.3V at 55 ns
Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
Low power consumption: STANDBY
- 66 µW max at 3.3V
Logic block diagram
r
A0
A1 V
CC
Selection guide
V
CC
Range
Min Typ
2
Max
10/6/00 ALLIANCE SEMICO
Product (V) (V) (V)
AS6VA25616 2.7 3.0 3.3
C I/O10 I/O11 A5 A6 I/O2 I/O3
DV
SS
I/O12 A17 A7 I/O4 V
CC
EV
CC
I/O13 NC A16 I/O5 V
SS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
HNCA8A9A10A1NC
Speed
Power Dissipation
Operating (I
CC
) Standby (I
SB1
)
256K × 16
Array
(4,194,304)
OE
CS
WE
Column decoder
Ro
w De
c
o
d
e
A2
A3
A4
A6
A7
A8
V
SS
A12
A5 A9
A1
0
A1
1
A1
4
A1
5
A1
6
A1
7
A13
Control circuit
I/O1–I/O8
I/O9–I/O16
UB
LB
I/O
buffer
Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
ESD protection ≥ 2000 volts
Latch-up current ≥ 200 mA
Pin arrangement (top view)
48-CSP Ball-Grid-Array Package
123456
ALBOE A0 A1 A2 NC
BI/O9UBA3 A4 CS I/O1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
A0
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
44-pin 400-mil TSOP II
21
22
A14
A13
UB
LB
I/O16
I/O15
2A3
3A2
4A1
1A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
October 2000
®
AS6VA25616
2.7V to 3.3V 256K × 16 Intelliwatt™ low-power CMOS SRAM with one chip enable
Features
• AS6VA25616
Intelliwatt™ active power circuitry
1.2V data retention
Equal access and cycle times
Easy memory expansion with CS, OE inputs
Copyright ©2000 Alliance Semiconductor. All rights reserved.
NDUCTOR 1
(ns) Max (mA) Max (µA)
55 2 20