©2001 Fairchild Semiconductor Corporation
November 2001
Rev. B, November 2001
S
S
W2N60B /

SSI
2N60B
SSW2N60B / SSI2N60B
600V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies.
Features
• 2.0A, 600V, R
DS(on)
= 5.0Ω @V
GS
= 10 V
• Low gate charge ( typical 12.5 nC)
• Low Crss ( typical 7.6 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter SSW2N60B / SSI2N60B Units
V
DSS
Drain-Source Voltage 600 V
I
D
Drain Current - Continuous (T
C
= 25°C) 2.0 A
- Continuous (T
C
= 100°C) 1.3 A
I
DM
Drain Current - Pulsed (Note 1) 6.0 A
V
GSS
Gate-Source Voltage ± 30 V
E
AS
Single Pulsed Avalanche Energy (Note 2) 120 mJ
I
AR
Avalanche Current (Note 1) 2.0 A
E
AR
Repetitive Avalanche Energy (Note 1) 5.4 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns
P
D
Power Dissipation (T
A
= 25°C) * 3.13 W
Power Dissipation (T
C
= 25°C) 54 W
- Derate above 25°C 0.43 W/°C
T
J
, T
stg
Operating and Storage Temperature Range -55 to +150 °C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
300 °C
Symbol Parameter Typ Max Units
R
θJC
Thermal Resistance, Junction-to-Case -- 2.32 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient * -- 40 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
* When mounted on the minimum pad size recommended (PCB Mount)
●
●
●
▲
!
!
!
◀
S
D
G
D
2
-PAK
SSW Series
I
2
-PAK
SSI Series
GS
D
GSD