© 2005 Fairchild Semiconductor Corporation DS500202 www.fairchildsemi.com
January 1999
Revised June 2005
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74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (c114 14 mA) and are connected to a
separate power supply pin (V
CC
-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the V
CC
-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
–A
8
/B
1
–B
8
transceiver
pins.
Features
a73 Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
a73 Translation capability allows outputs on the cable side to
interface with 5V signals
a73 All inputs have hysteresis to provide noise margin
a73 B and Y output resistance optimized to drive external
cable
a73 B and Y outputs in high impedance mode during power
down
a73 Inputs and outputs on cable side have internal pull-up
resistors
a73 Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
a73 Replaces the function of two (2) 74ACT1284 devices

Ordering Code
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74LVX161284MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVX161284MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
HD High Drive Enable Input (Active HIGH)
DIR Direction Control Input
A
1
–A
8
Inputs or Outputs
B
1
–B
8
Inputs or Outputs
A
9
–A
13
Inputs
Y
9
–Y
13
Outputs
A
14
–A
17
Outputs
C
14
–C
17
Inputs
PLH
IN
Peripheral Logic HIGH Input
PLH Peripheral Logic HIGH Output
HLH
IN
Host Logic HIGH Input
HLH Host Logic HIGH Output