October 1993
Revised January 1999
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© 1999 Fairchild Semiconductor Corporation DS011646.prf www.fairchildsemi.com
74ABT16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16543 16-bit transceiver contains two sets of D-
type latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. Each byte has separate control inputs, which can be
shorted together for full 16-bit operation.
Features
a73 Back-to-back registers for storage
a73 Bidirectional data path
a73 A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
a73 Separate control logic for each byte
a73 16-bit version of the ABT543
a73 Separate controls for data flow in each direction
a73 Guaranteed latchup protection
a73 High impedance glitch free bus loading during entire
power up and power down cycle
a73 Nondestructive hot insertion capability

Ordering Code:
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Order Number Package Number Package Description
74ABT16543CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16543CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OEAB
n
A-to-B Output Enable Input (Active LOW)
OEBA
n
B-to-A Output Enable Input (Active LOW)
CEAB
n
A-to-B Enable Input (Active LOW)
CEBA
n
B-to-A Enable Input (Active LOW)
LEAB
n
A-to-B Latch Enable Input (Active LOW)
LEBA
n
B-to-A Latch Enable Input (Active LOW)
A
0
–A
15
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs