1
1 G : Gate
2 S1 : Source1
3 S2 : Source2
4 D : Drain
FUJI POWER MOS FET
Fig.1
Ｐ矢視図参照
Fig.1
Ｐ矢視図
Note:1. Dimension shown in ( ) is
reference values.
注）１.（　）内寸法は参考値とする。
Special
specification
for customer
Trademark
Lot No.
Type name
ロットNo.
D
S2
G
S1
MARKING
OUT VIEW
外形寸法図
DIMENSIONS ARE IN MILLIMETERS.
MARKING
表示内容
CONNECTION
結線図
商標
特殊品記号
形名
表示内容
1 G : Gate
2 S1 : Source1
3 S2 : Source2
4 D : Drain
Item Symbol Ratings Unit
Drain-source voltage VDS 100
VDSX *5 70
Continuous drain current ID Tc=25
°C
±20
Ta=25
°C
±4.4
Pulsed drain current ID(puls] ±80
Gate-source voltage VGS ±30
Non-repetitive Avalanche current IAS *2 20
Maximum Avalanche Energy EAS *1 227
Maximum Drain-Source dV/dt dVDS/dt *4 20
Peak Diode Recovery dV/dt dV/dt *3 5
Max. power dissipation PD Tc=25
°C
50
Ta=25
°C
2.4 **
Operating and storage Tch +150
temperature range Tstg
Electrical characteristics (Tc =25°C unless otherwise specified)
Thermalcharacteristics
2SK3601-01
FUJI POWER MOSFET
N-CHANNEL SILICON POWER MOSFET
Features
High speed switching
Low on-resistance
No secondary breadown
Low driving power
Avalanche-proof
Applications
Switching regulators
UPS (Uninterruptible Power Supply)
DC-DC converters
Maximum ratings and characteristicAbsolute maximum ratings
(Tc=25°C unless otherwise specified)
Item Symbol Test Conditions
Zero gate voltage drain current IDSS
VDS=100V VGS=0V
VDS=80V VGS=0V
VGS=±30V
ID=10A VGS=10V
ID=10A VDS=25V
VCC=48V ID=10A
VGS=10V
RGS=10 Ω
Min. Typ. Max. Units
V
V
µA
nA
mΩ
S
pF
nC
A
V
ns
µC
ns
Min. Typ. Max. Units
Thermal resistance
Rth(ch-c) channel to case
Rth(ch-a) channel to ambient
Rth(ch-a) ** channel to ambient
2.5
87.0
52.0
°C/W
°C/W
Symbol
V(BR)DSS
VGS(th)
IGSS
RDS(on)
gfs
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
IAV
VSD
trr
Qrr
Item
Drain-source breakdown voltaget
Gate threshold voltage
Gate-source leakage current
Drain-source on-state resistance
Forward transcondutance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on time ton
Turn-off time toff
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Avalanche capability
Diode forward on-voltage
Reverse recovery time
Reverse recovery charge
Test Conditions
ID= 250
µ
A VGS=0V
ID= 250
µ
A VDS=VGS
Tch=25°C
Tch=125°C
VDS=0V
VDS=75V
VGS=0V
f=1MHz
VCC=50V
ID=20A
VGS=10V
L=100µH Tch=25°C
IF=20A VGS=0V Tch=25°C
IF=20A VGS=0V
-di/dt=100A/µs
Tch=25°C
V
V
A
A
A
V
A
mJ
kV/µs
kV/µs
W
°C
°C
100
3.0 5.0
25
250
10 100
47 62
612
730 1095
190 285
12 18
12 18
3.8 6
23 35
8.5 13
22 33
9 13.5
69
20
1.10 1.65
65
0.17
-55 to +150
Outline Drawings (mm)
Equivalent circuit schematic
Super FAP-G Series
*3 IF -ID, -di/dt=50A/µs, Vcc BVDSS, Tch 150°C
=
<
=
<
=
<
*1 L=681µH, Vcc=48V *2 Tch 150°C
=
<
*4 VDS 100V
<
=
www.fujielectric.co.jp/denshi/scd
*5 VGS=-30V
G : Gate
S2 : Source
D : Drain
S1 : Source
** Surface mounted on 1000mm
2
, t=1.6mm FR-4 PCB(Drain pad area : 500mm
2
)
** Surface mounted on 1000mm
2
, t=1.6mm FR-4 PCB(Drain pad area : 500mm
2
)