ADS852
器件描述：14-Bit, 65MHz Sampling ANALOG-TO-DIGITAL CONVERTER
器件厂商：BURR-BROWN [Burr-Brown Corporation]
文件大小：63.32KB，共5页
Sponsor by e络盟器件资料摘要：
14-Bit
Pipelined
A/D Core
Reference and
Mode Select
Reference Ladder
and Driver
Timing Circuitry
Error
Correction
Logic
3-State
Outputs
T/H
D0
D13
•
•
•
+V
S
ADS852
CLK
CLK
OESEL2 REFBV
REF
REFT VDRV
IN2Vp-p
2Vp-p
CM
(+2.5V)
SEL1
OVR
IN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1998 Burr-Brown Corporation PDS-1442 Printed in U.S.A. June, 1998
ADS852
®
14-Bit, 65MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
l HIGH DYNAMIC RANGE:
High SFDR: 100dB at 20MHz f
IN
High SNR: 75dB at 20MHz f
IN
l PREMIUM TRACK/HOLD:
High Bandwidth: 1GHz
Low Jitter: 0.25pS rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
l FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
DESCRIPTION
The ADS852 is a high-dynamic range 14-bit, 65MHz
pipelined analog-to-digital converter. It includes a high-
bandwidth linear track/hold that gives excellent spurious
performance up to and beyond the Nyquist rate. This high-
bandwidth track/hold also has a low jitter of only 0.25pS
rms, leading to excellent SNR performance. The clock input
can accept a low level differential sine wave or square wave
signal down to 0.5Vp-p, further improving the SNR perfor-
mance. It also accepts a single-ended clock signal and has
flexible threshold levels.
The ADS852 has a 4Vp-p differential input range (2Vp-p x
2 inputs, +16dBm) for optimum signal-to-noise ratio. The
differential operation gives the lowest even-order harmonic
components. A lower input voltage of 3Vp-p or 2Vp-p can
also be selected using the internal references, further opti-
mizing SFDR. Alternatively, a single-ended input range can
be used by tying the IN input to the common-mode voltage
if desired.
The ADS852 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front end signal conditioning circuitry. It also employs
digital error correction techniques to provide excellent dif-
ferential linearity for demanding imaging applications. The
ADS852 is available in a small 48-lead TQFP package.
PRELIMINARY INFORMATION
SUBJECT TO CHANGE
WITHOUT NOTICE
APPLICATIONS
l BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, NMT
l TEST INSTRUMENTATION
l CCD IMAGING
Pipelined
A/D Core
Reference and
Mode Select
Reference Ladder
and Driver
Timing Circuitry
Error
Correction
Logic
3-State
Outputs
T/H
D0
D13
•
•
•
+V
S
ADS852
CLK
CLK
OESEL2 REFBV
REF
REFT VDRV
IN2Vp-p
2Vp-p
CM
(+2.5V)
SEL1
OVR
IN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1998 Burr-Brown Corporation PDS-1442 Printed in U.S.A. June, 1998
ADS852
®
14-Bit, 65MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
l HIGH DYNAMIC RANGE:
High SFDR: 100dB at 20MHz f
IN
High SNR: 75dB at 20MHz f
IN
l PREMIUM TRACK/HOLD:
High Bandwidth: 1GHz
Low Jitter: 0.25pS rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
l FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
DESCRIPTION
The ADS852 is a high-dynamic range 14-bit, 65MHz
pipelined analog-to-digital converter. It includes a high-
bandwidth linear track/hold that gives excellent spurious
performance up to and beyond the Nyquist rate. This high-
bandwidth track/hold also has a low jitter of only 0.25pS
rms, leading to excellent SNR performance. The clock input
can accept a low level differential sine wave or square wave
signal down to 0.5Vp-p, further improving the SNR perfor-
mance. It also accepts a single-ended clock signal and has
flexible threshold levels.
The ADS852 has a 4Vp-p differential input range (2Vp-p x
2 inputs, +16dBm) for optimum signal-to-noise ratio. The
differential operation gives the lowest even-order harmonic
components. A lower input voltage of 3Vp-p or 2Vp-p can
also be selected using the internal references, further opti-
mizing SFDR. Alternatively, a single-ended input range can
be used by tying the IN input to the common-mode voltage
if desired.
The ADS852 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front end signal conditioning circuitry. It also employs
digital error correction techniques to provide excellent dif-
ferential linearity for demanding imaging applications. The
ADS852 is available in a small 48-lead TQFP package.
PRELIMINARY INFORMATION
SUBJECT TO CHANGE
WITHOUT NOTICE
APPLICATIONS
l BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, NMT
l TEST INSTRUMENTATION
l CCD IMAGING