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74AC241MTCX

器件描述:Octal Buffer/Line Driver with 3-STATE Outputs
器件厂商:FAIRCHILD [Fairchild Semiconductor]
文件大小:111.54KB,共8页
Sponsor by e络盟
器件资料摘要:
© 2005 Fairchild Semiconductor Corporation DS009942 www.fairchildsemi.com
November 1988
Revised March 2005
7
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• 74ACT241 O
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74AC241 74ACT241
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The AC/ACT241 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus-oriented transmitter or receiver which provides
improved PC board density.
Features
a73 I
CC
and I
OZ
reduced by 50%
a73 Non-inverting 3-STATE outputs drive bus lines or buffer
memory address registers
a73 Outputs source/sink 24 mA
a73 ACT241 has TTL-compatible inputs

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
Pin Descriptions
Truth Tables
H c32 HIGH Voltage Level
L c32 LOW Voltage Level
X c32 Immaterial
Z c32 High Impedance
FACTc165 is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC241SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC241SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC241MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC241PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT241SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT241SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT241MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT241PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
OE
1
3-STATE Output Enable Input
OE
2
3-STATE Output Enable Input (Active HIGH)
I
0
–I
7
Inputs
O
0
–O
7
Outputs
Inputs Outputs
OE
1
I
n
(Pins 12, 14, 16, 18)
LL L
LH H
HX Z
Inputs Outputs
OE
2
I
n
(Pins 3, 5, 7, 9)
HL L
HH H
LX Z