v6.0
40MX and 42MX FPGA Families
Features
High Capacity
• Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
High Performance
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
HiRel Features
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
Clock-to-Out 9.5 ns 9.5 ns 5.6 ns 6.1 ns 6.1 ns 6.3 ns
SRAM Modules
(64x4 or 32x8) ––– – –10
Dedicated Flip-Flops – – 348 624 954 1,230
Maximum Flip-Flops 147 273 516 928 1,410 1,822
Clocks 112 26
User I/O (maximum) 57 69 104 140 176 202
PCI ––– –YesYes
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
44, 68
100
80
–
–
–
44, 68, 84
100
80
–
–
–
84
100, 160
100
176
–
–
84
100, 160, 208
100
176
–
–
84
160, 208
–
176
–
–
–
208, 240
–
–
208, 256
272
January 2004 i
© 2004 Actel Corporation See the Actel website (www.actel.com) for the latest version of this datasheet.