UltraLogic™ 128-Macrocell Flash CPLD
fax id: 6139
CY7C374i
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1995 – Revised December 19, 1997
Features
• 128 macrocells in eight logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
—f
MAX
= 125 MHz
—t
PD
= 10 ns
—t
S
= 5.5 ns
—t
CO
= 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
• Pin compatible with the CY7C373i
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the FLASH370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Logic Block Diagram
7C374i-1
PIM
INPUT
MACROCELL
CLOCK
INPUTS
4 4
36
16 16
36
LOGIC
BLOCK 36
16 16
36
8 I/Os
36 36
36
16 16
36
16 16
32 32
41
INPUT/CLOCK
MACROCELLS
I/O
0
–I/O
7
A
INPUTS
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O
8
–I/O
15
I/O
16
–I/O
23
I/O
24
–I/O
31
I/O
56
–I/O
63
I/O
48
–I/O
55
I/O
40
–I/O
47
I/O
32
–I/O
39
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
Selection Guide
7C374i–125 7C374i–100 7C374i–83 7C374i–66 7C374iL–66
Maximum Propagation Delay
[1]
, t
PD
(ns) 10 12 15 20 20
Minimum Set-Up, t
S
(ns) 5.5 6 8 10 10
Maximum Clock to Output
[1]
, t
CO
(ns) 6.5 7 8 10 10
Typical Supply Current, I
CC
(mA) 125 125 125 125 75
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when VCCIO = 3.3V.