74VHC86NX
器件描述：Quad 2-Input Exclusive-OR Gate
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：75.97KB，共7页
Sponsor by e络盟器件资料摘要：
© 2005 Fairchild Semiconductor Corporation DS011517 www.fairchildsemi.com
November 1992
Revised February 2005
7
4
VH
C86
Quad 2-I
nput Excl
usive
-OR
Gat
e
74VHC86
Quad 2-Input Exclusive-OR Gate
General Description
The VHC86 is an advanced high speed CMOS Quad
Exclusive OR Gate fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as battery back up. This
circuit prevents device destruction due to mismatched sup-
ply and input voltages.
Features
a73 High Speed: t
PD
c32 4.8 ns (typ) at V
CC
c32 5V
a73 Low Power Dissipation: I
CC
c32 2 c80A (Max.) @ T
A
c32 25c113C
a73 High Noise Immunity: V
NIH
c32 V
NIL
c32 28% V
CC
(Min.)
a73 Power down protection is provided on all inputs
a73 Low Noise: V
OLP
c32 0.8V (Max.)
a73 Pin and Function Compatible with 74HC86
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Order Number
Package
Package Description
Number
74VHC86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC86SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC86MTCX_NL
(Note 1)
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
A
0
–A
3
Inputs
B
0
–B
3
Inputs
O
0
–O
3
Outputs
ABO
LLL
LHH
HL
HHL
November 1992
Revised February 2005
7
4
VH
C86
Quad 2-I
nput Excl
usive
-OR
Gat
e
74VHC86
Quad 2-Input Exclusive-OR Gate
General Description
The VHC86 is an advanced high speed CMOS Quad
Exclusive OR Gate fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as battery back up. This
circuit prevents device destruction due to mismatched sup-
ply and input voltages.
Features
a73 High Speed: t
PD
c32 4.8 ns (typ) at V
CC
c32 5V
a73 Low Power Dissipation: I
CC
c32 2 c80A (Max.) @ T
A
c32 25c113C
a73 High Noise Immunity: V
NIH
c32 V
NIL
c32 28% V
CC
(Min.)
a73 Power down protection is provided on all inputs
a73 Low Noise: V
OLP
c32 0.8V (Max.)
a73 Pin and Function Compatible with 74HC86
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Order Number
Package
Package Description
Number
74VHC86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC86SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC86MTCX_NL
(Note 1)
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names Description
A
0
–A
3
Inputs
B
0
–B
3
Inputs
O
0
–O
3
Outputs
ABO
LLL
LHH
HL
HHL