g36g88g74g88g86g87g3g21g19g19g20
g36g71g89g68g81g70g72g71g3g44g81g73g82g85g80g68g87g76g82g81
g38g82g83g92g85g76g74g75g87g3g139g3g36g79g79g76g68g81g70g72g3g54g72g80g76g70g82g81g71g88g70g87g82g85g17g3g36g79g79g3g85g76g74g75g87g86g3g85g72g86g72g85g89g72g71g17
g138
g36g54g21g28g47g57g20g25g19
g22g57g3g21g48g3g238g3g27g3g18g3g20g48g3g238g3g20g25g3g16g3g38g48g50g54g3g41g79g68g86g75g3g40g40g51g53g50g48
8/30/01; V.0.9.5 g36g79g79g76g68g81g70g72g3g54g72g80g76g70g82g81g71g88g70g87g82g85 P. 1 of 29
g41g72g68g87g88g85g72g86
• Organization: 2M×8 / 1M×16
Sector architecture
- One 16K; two 8K; one 32K; and thirty-one 64K byte sectors
- One 8K; two 4K; one 16K; and thirty-one 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
Single 2.7-3.6V power supply for read/write operations
Sector protection
High speed 70/80/90/120 ns address access time
Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
Hardware RESET pin
- Resets internal state machine to read mode
Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO (availability TBD)
CFI (Common Flash Interface) compliant
Detection of program/erase cycle completion
-DQ7 DATA polling
- DQ6 toggle bit
-RY/BY output
Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
Low V
CC
write lock-out below 1.5V
10 year data retention at 150C
100,000 write/erase cycle endurance
g47g82g74g76g70g3g69g79g82g70g78g3g71g76g68g74g85g68g80
X decoder
V
CC
V
SS
Cell matrix
Y decoder Y gating
Data latchChip enable
A
d
dr
es
s
la
t
c
h
Input/output
buffers
Sector protect/
Command
register
Program/erase
control
V
CC
detector
Erase voltage
generator
Program voltage
generator
Timer
A0–A19
CE
OE
STB
STB
Output enable
Logic
RY/BY
WE
RESET
DQ0–DQ15 (A-1)
switches
erase voltage
BYTE
g54g72g79g72g70g87g76g82g81g3g74g88g76g71g72
29LV160-70 29LV160-80 29LV160-90 29LV160-120 Unit
Maximum access time t
AA
70 80 90 120 ns
Maximum chip enable access time t
CE
70 80 90 120 ns
Maximum output enable access time t
OE
30 30 35 50 ns
g51g76g81g3g68g85g85g68g81g74g72g80g72g81g87
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
44-pin SO
21
22
DQ3
DQ11
A10
A11
A12
A13
2A18
3A17
4A7
1Reset
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A19
A8
A9
WE
A8 A9
A10 A11 A12 A13 A14 A15
A
1
6
BY
T
E
V
SS
D
Q
15/
A-
1
DQ7DQ1
4
A19
NCWE
RE
S
E
T
NCNC
RY
/
B
Y
A18
D
Q
2
DQ1
0
DQ3 DQ1
1
V
CC
DQ4 DQ1
2
DQ5 DQ6DQ1
3
1234567891011121314
4847464544434241403938373635
1516
3433
48-pin TSOP
A17
A7A6A5A4A3A2A1
A
0
CE V
SS
OE DQ0 DQ8 DQ1 DQ9
171819202122
323130292827
2324
2625
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g57
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g25
g19