© 2000 Fairchild Semiconductor Corporation DS006557 www.fairchildsemi.com
September 1986
Revised February 2000
DM74174
Hex/
Q
u
ad D-
T
y
pe Fl
ip-
F
l
op wi
th
Clear
DM74174
Hex/Quad D-Type Flip-Flop with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input.
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the posi-
tive-going edge of the clock pulse. Clock triggering occurs
at a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock
input is at either the HIGH or LOW level, the D input signal
has no effect at the output.
Features
a73 Contains six flip-flops with single-rail outputs
a73 Buffered clock and direct clear inputs
a73 Individual data input to each flip-flop
a73 Applications include:
Buffer/storage registers
Shift registers
Pattern generators
a73 Typical clock frequency 40 MHz
a73 Typical power dissipation per flip-flop 38 mW

Ordering Code:
Connection Diagram Function Table
(Each Flip-Flop)
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q
0
= The level of Q before the indicated steady-state input conditions were
established.
Order Number Package Number Package Description
DM74174 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
Clear Clock D Q
LXXL
H ↑ HH
H ↑ LL
HLXQ
0